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AT91SAM9261的ROMBoot启动片段

Posted on 2008-05-20 22:24 vsolo 阅读(1137) 评论(0)  编辑 收藏 引用 所属分类: MISC

AT91SAM9261中内部ROM有32K,可惜启动代码只用了不到8K的空间,目前看来还是有浪费之嫌的(想想当年51就寒碜)
上电启动代码的反汇编,只走了第一个S文件:

ROM:00400000                 AREA ROM, CODE, READWRITE, ALIGN=0
ROM:00400000                 ; ORG 0x400000
ROM:00400000                 CODE32
ROM:00400000                 B       loc_400020    //Reset
ROM:00400000 ; --------------------------------------------------------------------------------
ROM:00400004                 DCB 0xFE ;       //Other Exception vectors
ROM:00400005                 DCB 0xFF
ROM:00400006                 DCB 0xFF
ROM:00400007                 DCB 0xEA ;
ROM:00400008                 DCB 0x2F ;
ROM:00400009                 DCB    0
ROM:0040000A                 DCB    0
ROM:0040000B                 DCB 0xEA ;
ROM:0040000C                 DCB 0xFE ;
ROM:0040000D                 DCB 0xFF
ROM:0040000E                 DCB 0xFF
ROM:0040000F                 DCB 0xEA ;
ROM:00400010                 DCB 0xFE ;
ROM:00400011                 DCB 0xFF
ROM:00400012                 DCB 0xFF
ROM:00400013                 DCB 0xEA ;
ROM:00400014                 DCB 0xFE ;
ROM:00400015                 DCB 0xFF
ROM:00400016                 DCB 0xFF
ROM:00400017                 DCB 0xEA ;
ROM:00400018                 DCB 0xFE ;
ROM:00400019                 DCB 0xFF
ROM:0040001A                 DCB 0xFF
ROM:0040001B                 DCB 0xEA ;
ROM:0040001C                 DCB 0xFE ;
ROM:0040001D                 DCB 0xFF
ROM:0040001E                 DCB 0xFF
ROM:0040001F                 DCB 0xEA ;
ROM:00400020 ; --------------------------------------------------------------------------------
ROM:00400020
ROM:00400020 loc_400020                             
ROM:00400020                 MOV     SP, #0x328000   //stack setup
ROM:00400024                 LDR     R1, =0xFFFFFC00   //即LDR  R1, =AT91C_PMC_SCER ;(PMC) System Clock Enable Register
ROM:00400028                 LDR     R0, =0x4001
ROM:0040002C                 STR     R0, [R1,#0x20]   //即STR  R0, [R1,#MOR] ;(PMC) Main Oscillator Register
ROM:00400030                 MOV     R4, #1
ROM:00400034
ROM:00400034 loc_400034                             
ROM:00400034                 LDR     R3, [R1,#0x68]   //即LDR   R3, [R1,#SR] ;(PMC) Status Register
ROM:00400038                 AND     R3, R4, R3
ROM:0040003C                 CMP     R3, #1
ROM:00400040                 BNE     loc_400034    //等待主时钟振荡器稳定
ROM:00400044                 MOV     R0, #1
ROM:00400048                 STR     R0, [R1,#0x30]   //即STR   R0, [R1,#MCKR] ;(PMC) Master Clock Register
ROM:0040004C                 MOV     R4, #8
ROM:00400050
ROM:00400050 loc_400050                             
ROM:00400050                 LDR     R3, [R1,#0x68]   //读取PMC状态
ROM:00400054                 AND     R3, R4, R3
ROM:00400058                 CMP     R3, #8
ROM:0040005C                 BNE     loc_400050
ROM:00400060                 ADR     R2, off_400094   //等待芯片时钟稳定
ROM:00400064                 LDMIA   R2, {R0,R1,R3,R4}
ROM:00400068                 CMP     R0, R1
ROM:0040006C                 BEQ     loc_400080
ROM:00400070
ROM:00400070 loc_400070                             
ROM:00400070                 CMP     R1, R3    //copy RW section to IRAM
ROM:00400074                 LDRCC   R2, [R0],#4
ROM:00400078                 STRCC   R2, [R1],#4
ROM:0040007C                 BCC     loc_400070
ROM:00400080
ROM:00400080 loc_400080                             
ROM:00400080                 MOV     R2, #0
ROM:00400084
ROM:00400084 loc_400084                            
ROM:00400084                 CMP     R3, R4    //copy ZI section to IRAM and Zero init
ROM:00400088                 STRCC   R2, [R3],#4
ROM:0040008C                 BCC     loc_400084
ROM:00400090                 B       loc_4000A4
ROM:00400090 ; --------------------------------------------------------------------------------
ROM:00400094 off_400094      DCD 0x401E9C     //|Image$$RO$$Limit|
ROM:00400098                 DCB    0     //|Image$$RW$$Base|
ROM:00400099                 DCB 0x70 ; p     
ROM:0040009A                 DCB 0x32 ; 2
ROM:0040009B                 DCB    0     
ROM:0040009C                 DCB 0x10     //|Image$$ZI$$Base|
ROM:0040009D                 DCB 0x70 ; p
ROM:0040009E                 DCB 0x32 ; 2
ROM:0040009F                 DCB    0     
ROM:004000A0                 DCB 0x88 ; ?     //|Image$$ZI$$Limit|
ROM:004000A1                 DCB 0x70 ; p
ROM:004000A2                 DCB 0x32 ; 2
ROM:004000A3                 DCB    0
ROM:004000A4 ; --------------------------------------------------------------------------------
ROM:004000A4
ROM:004000A4 loc_4000A4                             
ROM:004000A4                 LDR     R0, =sub_401690
ROM:004000A8                 MOV     LR, PC
ROM:004000AC                 BX      R0
ROM:004000B0                 LDR     R0, =sub_40066C
ROM:004000B4                 MOV     LR, PC
ROM:004000B8                 BX      R0
ROM:004000BC                 MRC     p15, 0, R5,c1,c0
ROM:004000C0                 MOV     R6, #0x1000
ROM:004000C4                 ORR     R5, R5, R6
ROM:004000C8                 MCR     p15, 0, R5,c1,c0
ROM:004000CC
ROM:004000CC loc_4000CC                             
ROM:004000CC                 LDR     R0, =sub_401338
ROM:004000D0                 MOV     LR, PC
ROM:004000D4                 BX      R0     //Jump to main Function
ROM:004000D8
ROM:004000D8 loc_4000D8                             
ROM:004000D8                 B       loc_4000D8    //Normally, never occur.

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