Posted on 2010-06-14 07:56 王小明
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will normally use a word aligned address. However, an
address offset from a word boundary will cause the data to be
rotated into the register so that the addressed byte occupies
bits 0 to 7. This means that half-words accessed at offsets 0
and 2 from the word boundary will be correctly loaded into
bits 0 through 15 of the register. Two shift operations are then
required to clear or to sign extend the upper 16 bits. This is
illustrated in Figure 5-15: Little Endian offset addressing on
A word store (STR) should generate a word aligned address.
The word presented to the data bus is not affected if the
address is not word aligned. That is, bit 31 of the register
being stored always appears on data bus output 31.